Multiprocessing systems with multiple shared resources are becoming increasingly commonplace. Such multiprocessing systems include, e.g., symmetric multiprocessing (SMP) chip fabrics having multiple processing units or processors and shared memory. A crossbar switch links the multiple processors to the shared memory. Firmware and/or circuitry in the crossbar switch arbitrates access to the shared memory.
Crossbar links may operate at a variety of different frequencies, e.g., based on the different clock speeds of the processors. The crossbar links are often synchronized so that the faster links do not always override the slower links when arbitrating for access to the shared memory.
The crossbar switch has to route an entire data packet before allowing other packets to arbitrate. Therefore, one method for synchronizing the links in a crossbar switch is to introduce invalid micropackets or “bubbles” into data packets coming from the slower processors. The bubbles serve as placeholders keeping the crossbar from switching to data packets arriving from the faster processors. However, introducing bubbles into data packets increases the latency of all packets through the crossbar, decreasing overall performance of the multiprocessing system.